Secure and Reliable VLSI Designs
暫譯: 安全可靠的VLSI設計

Over the past few decades, programmable logic devices (PLD) such as complex PLDs (CPLD) and field programmable gate arrays (FPGA) are extensively used as the basic building modules in most digital systems due to their robust features such as high density, field re- programmability and faster time-to-market. In addition, usage of PLDs in design reduces discrete integrated circuits (IC) population and associated interconnections on printed circuit board. This, in turn, increases the reliability of PLD-based systems. However, when features such as unit cost, speed, power are considered, application specific integrated circuits (ASIC) are most suitable devices. They also address the problem of fast obsolescence associated with PLDs. Hence, it is clearly evident that electronic systems have proliferated over the past few decades to the point that most aspects of daily life are aided or affected by the automation, control, monitoring, or computational power provided by ICs.

A typical PLD design cycle includes programming using hardware description language (HDL), synthesis (netlist generation), simulation, mapping to technology, place and route (PAR), generation of configuration bitstream and finally programming the target device. In general, ASICs follow the same design flow as PLDs till synthesis by converting the target design using basic digital components. Further, it has various stages such as layout formation using standard cell library, mask generation, chip fabrication and package with post-silicon testing.

Together with featured advantages of PLD and ASIC based digital designs, many security concerns have arisen; especially, the ability to trust these ICs to perform their specified operation (and only their specified operation) has always been a security concern and has recently become a more active topic of research. The increased deployment of such devices in safety critical applications or sensitive areas, such as nuclear power plant, space, military, health care, treasury and border control has also heightened the need to develop the secure and reliable very large-scale integration (VLSI) designs that ensures the design and data security. The goal of this thesis is to investigate the potential hardware security threats in VLSI device based safety critical applications, in particular, to identify key areas of improvement in hardware security and to suggest solutions for the same with their associated overhead.