Verilog Designer's Library (IE-Paperback)
Bob Zeidman, Robert M. Zeidman
- 出版商: Prentice Hall
- 出版日期: 1999-06-14
- 售價: $1,007
- 語言: 英文
- 頁數: 432
- ISBN: 9867594290
- ISBN-13: 9789867594297
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相關分類:
Verilog
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商品描述
Verilog Developer's Librarybrings together an extensive library of Verilog routines, each designed to simplify and streamline a key task in integrated circuit design. Fully documented, well organized, and provided royalty-free on CD-ROM for your personal use, these routines offer the potential to dramatically reduce your development time -- and your time to market. And if you're relatively new to Verilog, these routines also make an outstanding tutorial.KEY TOPICS:The routines are organized according to functionality, with each chapter addressing a widely-used function, including state machines, memories, memory controllers, data flow, error detection and correction, and many more. Both behavioral and RTL models are provided. From linear feedback shift registers to encrypter/decrypters, checksum and CRC code to SRAM controller code, this book offers sophisticated solutions to problems you would otherwise have to write new code to solve. Each routine is thoroughly, clearly explained -- so you'll find it exceptionally easy and convenient to adapt them as needed. The accompanying CD-ROM contains all the book's source code. MARKET:For Verilog users familiar with the basic structure of the language and want to develop real applications. Titles include: design specialists, analysts, trainers, consultants, developers, and system integrators.
Table of Contents
I. CODING TECHNIQUES.
2. Behavioral Coding Techniques.
3. RTL Coding Techniques.
4. Synthesis Issues.
5. Simulation Issues.
II. BASIC BUILDING BLOCKS.
7. The Shift Register.
8. The Counter.
9. The Adder.
III. STATE MACHINES.
11. The Mealy State Machine.
12. The One-Hot State Machine for FPGAs.
IV. MISCELLANEOUS COMPLEX FUNCTIONS.
14. The Encrypter/Decrypter.
15. The Phase Locked Loop (PLL).
16. The Unsigned Integer Multiplier.
17. The Signed Integer Multiplier.
V. ERROR DETECTION AND CORRECTION.
19. Hamming Code Logic.
20. The Checksum.
21. The Cyclic Redundancy Check (CRC).
VI. MEMORIES.
23. The Dual Port RAM.
24. The Synchronous FIFO.
25. The Synchronizing FIFO.
VII. MEMORY CONTROLLERS.
27. The Synchronous SRAM Controller.
28. The DRAM Controller.
29. The Fast Page Mode DRAM Controller.
Appendix A: Resources.
Index.