計算機系統貫通課程實踐教材（RISC-V架構）
常瑞、申文博、吳磊、周亞金
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目錄
第1部分 計算機系統I——單周期CPU設計 ...................................................................................... 1
第1章 SysI-Lab1實驗準備 ...................................................................................... 3
1.1實驗工具 ...................................................................................... 3
1.2背景知識
......................................................................................... 4
1.2.1
FPGA的發展歷程................................................................. 4
1.2.2
Verilog基礎知識 ................................................................... 6
1.3實驗環境配置
.................................................................................12
1.3.1
Linux環境配置 ....................................................................12
1.3.2
SPICE仿真反相器 ...............................................................13
1.3.3
Logisim電路仿真 .................................................................15
1.4
Verilator仿真測試 ..........................................................................16
1.5
Vivado操作流程.............................................................................18
1.5.1 FPGA上的 Verilog實踐.......................................................28
1.
5.2以二選一多路選擇器為例 ......................................................35 思考及練習 ............................................................................................36
第 2章 SysI-Lab2多路選擇器 ..................................................................38
2.1實驗工具
........................................................................................38
2.
2多路選擇器設計 ..............................................................................38
2.2.1基本概念
..............................................................................38
2.
2.2電路級別的實現....................................................................39
2.
2.3四路選擇器的實現 ................................................................39
2.3實驗步驟
........................................................................................41 思考及練習 ............................................................................................41
第 3章 SysI-Lab3七段數碼管 ..................................................................42
3.1實驗工具
........................................................................................42
3.2背景知識
........................................................................................42
3.
2.1復合多路選擇器....................................................................42
3.2.2譯碼器
.................................................................................43
計算機系統貫通課程實踐教材（RISC-V架構）
3.2.3時鐘分頻器 ..........................................................................43
3.2.4 NEXYS A7-100T七段管 ......................................................43
3.3實驗步驟 ........................................................................................45 思考及練習 ............................................................................................46
第 4章 SysI-Lab4全加減法器 ..................................................................47
4.1實驗工具 ........................................................................................47
4.2加法器設計.....................................................................................47
4.2.1加法器實驗原理....................................................................47
4.2.2加法器實驗步驟....................................................................50
4.3加減法器設計 .................................................................................51
4.3.1加減法器實驗原理 ................................................................51
4.3.2 64b加減法器實驗步驟 ..........................................................52 思考及練習 ............................................................................................52
第 5章 SysI-Lab5時序電路設計 ...............................................................53
5.1實驗工具 ........................................................................................53
5.2時序電路設計基礎...........................................................................53
5.2.1有限狀態機 ..........................................................................53
5.2.2計數器 .................................................................................55
5.2.3分頻器 .................................................................................55
5.3計時器設計.....................................................................................56
5.3.1 4位二進制計數器 .................................................................56
5.3.2 2位 BCD碼計數器 ..............................................................57
5.3.3計時器實驗步驟....................................................................57
5.4乘法器設計.....................................................................................58
5.4.1乘法器實驗原理....................................................................58
5.4.2 Booth算法 ..........................................................................60
5.4.3乘法器實驗步驟....................................................................61 思考及練習 ............................................................................................62
第 6章 SysI-Lab6卷積核實現 ..................................................................63
6.1實驗工具 ........................................................................................63
6.2背景知識 .......................................................................................63
6.2.1移位寄存器 ..........................................................................63
6.2.2 SystemVerilog語法...............................................................64
6.2.3 Ready-Valid握手 .................................................................66
6.3實驗原理 ........................................................................................67
7.5.1理解跳轉表 ..........................................................................86
7.5.2回顧冒泡排序算法 ................................................................87
7.5.3理解簡單 RISC-V程序 .........................................................87
7.5.4理解遞歸匯編程序 ................................................................88
7.5.5理解 switch語句產生的跳轉表 ..............................................89
7.6實驗步驟 ........................................................................................90
7.6.1冒泡排序的匯編實現 .............................................................90
7.6.2斐波那契數列的匯編實現 ......................................................90
7.6.3通過調試破解密鑰 ................................................................91
7.6.4 RISC-V Binary Bomb...........................................................92 思考及練習 ............................................................................................93
第 8章 SysI-Lab8單周期 CPU設計........................................................94
8.1實驗工具 ........................................................................................94
8.2背景知識 ........................................................................................94
8.2.1 RISC-V指令格式 .................................................................94
8.2.2數據通路..............................................................................95
8.2.3控制單元..............................................................................97
8.3 RISC-V基礎指令 ......................................................................... 101
8.4實驗原理 ...................................................................................... 114
8.4.1 Memory設計 ..................................................................... 114
8.4.2數據通路設計 ..................................................................... 116
數據冒險............................................................................
9.3.2實現暫停機制 ..................................................................... 128
9.4 DRAM和 BRAM的區別.............................................................. 128
9.5 BRAM的使用.............................................................................. 129
9.6實驗目標 ...................................................................................... 130
9.7實驗步驟 ...................................................................................... 131 思考及練習 .......................................................................................... 132
第 10章 SysII-Lab2流水線冒險的解決.................................................... 133
10.1實驗工具 .................................................................................... 133
10.2實驗原理 .................................................................................... 133
10.2.1流水線的旁路機制 ........................................................... 133
10.2.2 Axi-lite總線協議 ............................................................ 134
10.3實驗步驟 .................................................................................... 136 思考及練習 .......................................................................................... 136
第 11章 SysII-Lab3卷積加速器.............................................................. 137
11.1實驗工具 .................................................................................... 137
11.2實驗原理 .................................................................................... 137
11.2.1外設編程接口.................................................................. 137
11.2.2 MMIO機制及定義 .......................................................... 138
11.2.3卷積加速器的 I/O映射及操作 ......................................... 139
實驗工具 ....................................................................................
13.2背景知識 .................................................................................... 150
13.2.1 RISC-V中的中斷和異常.................................................. 150
13.2.2上下文處理 ..................................................................... 152
13.2.3異常處理程序和時鐘中斷 ................................................. 152
13.3實驗步驟 .................................................................................... 152
13.3.1準備工程 ........................................................................ 152
13.3.2開啟異常處理.................................................................. 154
13.3.3實現上下文切換 .............................................................. 155
13.3.4實現異常處理函數 ........................................................... 156
13.3.5實現時鐘中斷相關函數 .................................................... 156
13.3.6實驗樣例 ........................................................................ 157 思考及練習 .......................................................................................... 157
第 14章 SysII-Lab6異常流水線.............................................................. 158
14.1實驗工具 .................................................................................... 158
14.2實驗原理 .................................................................................... 158
14.2.1 RISC-V特權級 ............................................................... 158
14.2.2控制和狀態寄存器 ........................................................... 158
14.2.3異常和中斷 ..................................................................... 159
14.3異常流水線設計 .......................................................................... 162
14.3.1實現 CSR指令................................................................ 162
15.3.4實驗樣例 ........................................................................ 174 思考及練習 .......................................................................................... 176
第 16章 SysII-Lab8軟硬件協同的嘗試.................................................... 177
16.1實驗工具 .................................................................................... 177
16.2實驗原理 .................................................................................... 177
16.2.1整體架構設計.................................................................. 177
16.2.2硬件外圍設計.................................................................. 178
16.3編譯內核 .................................................................................... 178
16.4外圍準備 .................................................................................... 179
16.4.1 Bootloader代碼 .............................................................. 179
16.4.2生成下板代碼.................................................................. 180
16.4.3建立工程文件.................................................................. 180
16.4.4觀察下板現象.................................................................. 181
16.4.5 Vivado仿真運行 ............................................................. 182
16.5實驗步驟 .................................................................................... 182 思考及練習 .......................................................................................... 182
第 3部分計算機系統 III——定制化內核 + CPU綜合設計 .............183
第 17章 SysIII-Lab1動態分支預測 ......................................................... 185
17.1實驗工具 .................................................................................... 185
18.2.4 Cache與 Memory的數據傳輸.......................................... 196
18.3 Cache控制邏輯 .......................................................................... 198
18.3.1初始化 IDLE狀態........................................................... 199
18.3.2讀事務執行 READ狀態 .................................................. 199
18.3.3寫事務執行 WRITE狀態 ................................................ 200
18.4 Cache的完整結構 ....................................................................... 201
18.5實驗步驟 .................................................................................... 203
18.5.1實驗目標 ........................................................................ 203
18.5.2仿真測試 ........................................................................ 204
18.5.3上板驗證 ........................................................................ 205 思考及練習 .......................................................................................... 205
第 19章 SysIII-Lab3 RV64虛擬內存管理 ............................................... 206
19.1實驗工具 .................................................................................... 206
19.2虛擬內存布局.............................................................................. 206
19.3 SATP寄存器.............................................................................. 207
19.4虛實地址轉換.............................................................................. 208
19.4.1虛擬地址和物理地址........................................................ 208
19.4.2 RISC-V Sv39模式頁表項 ................................................ 208
19.4.3 RISC-V地址轉換............................................................ 209
19.5實驗步驟 .................................................................................... 209
20.4.3中斷處理 ........................................................................ 221
20.4.4添加系統調用.................................................................. 223
20.4.5修改內核啟動.................................................................. 223
20.4.6編譯及測試 ..................................................................... 223 思考及練習 .......................................................................................... 224
第 21章 SysIII-Lab5 RV64缺頁異常處理 ............................................... 225
21.1實驗工具 .................................................................................... 225
21.2背景知識 .................................................................................... 225
21.2.1虛擬內存管理.................................................................. 225
21.2.2缺頁異常 ........................................................................ 226
21.3實驗步驟 .................................................................................... 227
21.3.1準備工程 ........................................................................ 227
21.3.2實現虛擬內存管理 ........................................................... 228
21.3.3任務初始化 ..................................................................... 230
21.3.4實現缺頁異常處理 ........................................................... 230
21.3.5編譯及測試 ..................................................................... 231 思考及練習 .......................................................................................... 232
第 22章 SysIII-Lab6 fork機制............................................................... 233
22.1實驗工具 .................................................................................... 233
22.2 fork基礎知識 ............................................................................. 233
23.2.1 RISC-V Sv39分頁模式.................................................... 241
23.2.2 Axi-lite總線模型 ............................................................ 243
23.2.3 MMU模塊 ..................................................................... 243
23.3實驗步驟 .................................................................................... 244
23.3.1實驗目標 ........................................................................ 244
23.3.2仿真測試 ........................................................................ 244
23.3.3上板驗證 ........................................................................ 244 思考及練習 .......................................................................................... 244
第 24章 SysIII-Lab8完成自己的計算機系統 ............................................ 245
24.1實驗工具 .................................................................................... 245
24.2實驗目標 .................................................................................... 245
24.3實驗原理 .................................................................................... 246
24.3.1用戶態實現及中斷完善 .................................................... 246
24.3.2地址轉換後備緩沖器........................................................ 246
24.3.3 MMIO與外設................................................................. 247
24.4設計範例 .................................................................................... 247
24.4.1範例一：指令集擴展........................................................ 247
24.4.2範例二：運行較為完善的 Kernel ...................................... 252 思考及練習 .......................................................................................... 259
第4部分 附錄及常見問題.................................. 261
附錄A 硬件描述語言常見語句及電路圖 ..................................263
附錄B 配置IP核..................................275
附錄C 常見問題..................................287
參考文獻..................................294
