Introduction to Systemverilog (Hardcover)
暫譯: SystemVerilog 入門 (精裝版)

Ashok Mehta is an ASIC/CPU design and verification engineer with over 30 years of experience in the semiconductor industry. He has worked at companies such as DEC, Data General, Intel, Applied Micro and TSMC. He was an early member of the Verilog technical subcommittees. He is the holder of 19 US Patents in the field of ASIC and 3DIC design and verification. He is also the author of two popular books, one on "SystemVerilog Assertions and Functional Coverage" and second on "ASIC Functional Design Verification - A guide to technologies and methodologies". His current interest include 3DIC semiconductor design verification, System Level Modeling (Virtual Platform) and verification methodologies in general.

Ashok Mehta 是一位具有超過 30 年半導體產業經驗的 ASIC/CPU 設計與驗證工程師。他曾在 DEC、Data General、Intel、Applied Micro 和 TSMC 等公司工作。他是 Verilog 技術小組的早期成員之一。他在 ASIC 和 3DIC 設計與驗證領域擁有 19 項美國專利。他也是兩本熱門書籍的作者，一本是《SystemVerilog Assertions and Functional Coverage》，另一本是《ASIC Functional Design Verification - A guide to technologies and methodologies》。他目前的興趣包括 3DIC 半導體設計驗證、系統級建模（虛擬平台）以及一般的驗證方法。