Digital Systems Design and Practice: Using Verilog HDL and FPGAs (美國原版)

With the advance of semiconductor and communication technologies, the use of systemon-a-chip (SoC) has become an essential technique to decrease product costs. To design and implement an SoC-based product, it proves necessary to totally or partly rely on the hardware description language (HDL) synthesis flow and field programmable gata array (FPGA) devices or cell libraries. As a consequence, it has become an important attainment for electrical engineers to develop a good understanding of the key issues of HDL design flows based on FPGA devices or cell libraries. To achieve this, this book addresses the need for teaching such a topic based on Verilog HDL and FPGAs. This book, Digital System Designs and Practices: Using Verilog HDL and FPGAs, aim to be used as a text for students and as a reference book for professionals or a self-study book for readers. For classroom use, each chapter includes many worked examples and review questions for helping readers test their understanding of the contents. In addition, throughout the book, an abundance of worked examples are provided for helping readers realize the basic features of Verilog HDL and grasp the essentials of digital system designs as well. The contents of this book largely stem from the course FPGA System Designs and Practices, offered at our campus over the past decade. This course is an undergraduate elective and the first-year graduate course. This book is so structured that it can be used as a sequence of courses, including Hardware Description Language, FPGA System Designs and Practices, Digital System Designs, Advanced Digital System Designs, and others. HDL-based design has become an essential technique for modern digital systems. This book focuses on developing, verifying, and synthesizing designs of practical digital systems using the most widely used hardware description Language: Verilog HDL and FPGAs. The main features of this book are: -- Explains how to perform synthesis and verification to achieve optimized synthesis results and compiler times -- Offers complete coverage of Verilog HDL syntax -- Illustrates the entire design and verification flow using an FPGA case study -- Presents many real-world worked design examples -- Gives readers deeper understanding with review questions in each section and end-of-chapter problems -- Emphasizes design/implementation tradeoff options, with coverage of ASICs and FPGAs