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商品描述
Since register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design.
商品描述(中文翻譯)
由於寄存器傳輸級（RTL）設計不僅僅是關於成為一位優秀的工程師，更重要的是了解您工作所帶來的下游影響，本書解釋了設計決策的影響，這些決策可能在產品生命周期的後期引發與可測試性、跨時鐘域的數據同步、可合成性、功耗、可路由性等相關的問題，這些問題都取決於RTL最初的編寫方式。讀者將從這些主題的基本原理中獲得高度實用的見解，並將獲得有關在RTL設計過程中需要遵循的必要保障措施的明確指導。
