Writing Testbenches: Functional Verification of HDL Models, 2/e (Hardocver)

Janick Bergeron

Writing Testbenches: Functional Verification of HDL Models, 2/e (Hardocver)

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商品描述

The Second Edition of Writing Testbenches, Functional Verification of HDL Models presents the latest verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems.

From the Foreword:

Building on the first edition, " ...the most successful and popular contemporary verification textbook", the author raises the verification level of abstraction by introducing coverage-driven constrained random transaction-level self-checking testbenches - all made possible through the introduction of hardware verification languages (HVLs) such as e from Verisity and OpenVera from Synopsys...." Harry Foster, Chief Architect, Verplex Systems, Inc.

Topics included in the new Second Edition:

  • Discussions on OpenVera and e;
  • approaches for writing constrainable random stimulus generators;
  • strategies for making testbenches self-checking;
  • a clear blueprint of a verification process that aims for first time success;
  • recent advances in functional verification such as coverage-driven verification process;
  • VHDL and Verilog language semantics;
  • the semantics are presented in new verification-oriented languages
  • techniques for applying stimulus and monitoring the response of a design;
  • behavioral modeling using non-synthesizeable constructs and coding style;
  • updated for Verilog 2001.

Contents：

About the Cover. Foreword. Preface. Why This Book Is Important. What This Book Is About. What Prior Knowledge You Should Have. Reading Paths. Choosing a Language: VHDL vs. Verilog. Hardware Verification Languages. And the Winner is... For More Information. Acknowledgements.

  • 1: What is Verification? What is a Testbench? The Importance of Verification. Reconvergence Model. The Human Factor. What Is Being Verified? Functional Verification Approaches. Testing Versus Verification. Design and Verification Reuse. The Cost of Verification. Summary.
  • 2: Verification Tools. Linting Tools. Simulators. Verification Intellectual Property. Waveform Viewers. Code Coverage. Functional Coverage. Verification Languages. Assertions. Revision Control. Issue Tracking. Metrics. Summary.
  • 3: The Verification Plan. The Role of the Verification Plan. Levels of Verification. Verification Strategies. From Specification to Features. Directed Testbenches Approach. Coverage-Driven Random-Based Approach. Summary.
  • 4: High-Level Modeling. Behavioral versus RTL Thinking. You Gotta Have Style! Structure of Behavioral Code. Data Abstraction. Object-Oriented Programming. Aspect-Oriented Programming. The Parallel Simulation Engine. Race Conditions. Verilog Portability Issues. Summary.
  • 5: Stimulus and Response. Reference Signals. Simple Stimulus. Simple Output. Complex Stimulus. Bus-Functional Models. Response Monitors. Transaction-Level Interface. Summary.
  • 6: Architecting Testbenches. Test Harness. VHDL Test Harness. Design Configuration. Self-Checking Testbenches. Directed Stimulus. Random Stimulus. Summary.
  • 7: Simulation Management. Behavioral Models. Pass or Fail? Managing Simulations. Regression. Summary.
  • APPENDIX A: Coding Guidelines. Directory Structure. General Coding Guidelines. Naming Guidelines. HDL Coding Guidelines.
  • APPENDIX B: Glossary. Afterwords. Index.

商品描述(中文翻譯)

《寫作測試台架，HDL模型的功能驗證》第二版介紹了最新的驗證技術，以生產完全功能的首片硅片ASIC、片上系統(SoC)、板卡和整個系統。

從前言中可以看到：在第一版的基礎上，作者通過引入基於覆蓋率驅動的受限隨機事務級自檢測台架，提高了驗證的抽象層次，這一切都得益於硬體驗證語言(HVLs)的引入，例如Verisity的e和Synopsys的OpenVera。Harry Foster, Verplex Systems, Inc.的首席架構師評價此書為「最成功和最受歡迎的當代驗證教材」。

新版的主題包括：
- 對OpenVera和e的討論；
- 撰寫可限制隨機刺激生成器的方法；
- 使測試台架自檢的策略；
- 旨在首次成功的驗證流程的明確藍圖；
- 覆蓋率驅動驗證流程等功能驗證的最新進展；
- VHDL和Verilog語言語義；
- 以新的驗證導向語言呈現語義；
- 應用刺激和監控設計響應的技術；
- 使用不可合成構造和編碼風格進行行為建模；
- 针对Verilog 2001進行更新。

內容包括：
- 封面介紹、前言、序言、本書的重要性、本書的內容、需要的先備知識、閱讀路徑、選擇語言：VHDL vs. Verilog、硬體驗證語言、更多資訊、致謝；
- 第一章：什麼是驗證？什麼是測試台架？驗證的重要性。重新匯聚模型。人為因素。正在驗證什麼？功能驗證方法。測試與驗證。設計和驗證的重複使用。驗證的成本。總結；
- 第二章：驗證工具。Linting工具。模擬器。驗證智慧財產。波形查看器。代碼覆蓋率。功能覆蓋率。驗證語言。斷言。修訂控制。問題追蹤。指標。總結；
- 第三章：驗證計劃。驗證計劃的角色。驗證層次。驗證策略。從規格到功能。定向測試台架方法。覆蓋率驅動的隨機方法。總結；
- 第四章：高層建模。行為思維與RTL思維。你必須有風格！行為代碼的結構。數據抽象。面向對象編程。面向方面的編程。並行模擬引擎。競態條件。Verilog的可移植性問題。總結；
- 第五章：刺激和響應。參考信號。簡單刺激。簡單輸出。複雜刺激。總線功能模型。響應監控。事務級接口。總結；
- 第六章：測試台架架構。測試鉤子。VHDL測試鉤子。設計配置。自檢測台架。定向刺激。隨機刺激。總結；
- 第七章：模擬管理。行為模型。通過或失敗？管理模擬。回歸。總結；
- 附錄A：編碼指南。目錄結構。一般編碼指南。命名指南。HDL編碼指南；
- 附錄B：詞彙表。結語。索引。

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