Circuit Techniques for Low-Voltage and High-Speed A/d Converters (Hardcover)

Mikko E. Waltari, Kari A.I. Halonen

Circuit Techniques for Low-Voltage and High-Speed A/d Converters (Hardcover)

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering. The throughput of ADCs can be increased by using parallelism. This is demonstrated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. Circuit Techniques for Low-Voltage and High-Speed A/D Converters presents a total of seven prototypes: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO techniques. This monograph will prove to be a useful reference for both academics and professionals whom are active in the Analog Circuit Design and Communications field.

商品描述(中文翻譯)

隨著電子應用領域中數位化的增加，從電信系統到消費性電子產品，需要具有更高取樣率、更高解析度和更低功耗的類比數位轉換器（ADC）。集成電路技術的演進在一定程度上有助於滿足這些要求，提供更快的設備並實現更複雜的功能，但同時也帶來了新的挑戰，其中最重要的是供應電壓的降低。基於開關電容（SC）技術，流水線架構最成功地利用了CMOS技術的特點，實現了高速高解析度的ADC。對供應電壓和技術尺度對SC電路的影響進行了分析，結果顯示，至少在未來幾個技術世代中可以期望到一些好處。運算放大器是SC電路中的核心組件，因此對其拓撲和低電壓能力進行了比較。眾所周知，SC技術在其標準形式下不適用於非常低的供應電壓，主要是因為開關控制電壓不足。研究了兩種低電壓改進方法：開關引導和開關運算放大器（SO）技術。提出了改進的電路結構。介紹了兩個使用SO技術的ADC原型，而引導引導開關則用於其他三個原型。ADC的一個組成部分是前端取樣保持（S/H）電路。在高信號頻率下，其線性度主要由所使用的開關決定。介紹了S/H架構的綜述，並研究了通過引導引導來實現開關線性化的方法，並應用於兩個原型中。另一個重要參數是取樣時鐘抖動，通過精心設計的時鐘生成和緩衝來進行分析和最小化。通過使用並行處理，可以增加ADC的吞吐量。在電路級別上，通過雙取樣技術來實現，該技術應用於S/H電路和流水線ADC。介紹了雙取樣中的非理想性分析。在系統級別上，並行處理用於時間交錯ADC。並行信號路徑的不匹配會產生誤差，為了消除這些誤差，開發了一個時間偏移不敏感的取樣電路和數字偏移校準。《低電壓和高速A/D轉換器的電路技術》總共提供了七個原型：兩個雙取樣S/H電路，一個時間交錯ADC，一個IF取樣自校準流水線ADC，一個具有去雜訊器的電流開關DAC，以及兩個使用SO技術的流水線ADC。這本專著將對從事模擬電路設計和通信領域的學術界和專業人士都是一個有用的參考資料。

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