Boolean Circuit Rewiring: Bridging Logical and Physical Designs Hardcover
暫譯: 布林電路重繞:邏輯與物理設計的橋接 平裝本
Tak-Kei Lam, Wai-Chung Tang, Xing Wei, Yi Diao, David Yu-Liang Wu
- 出版商: Wiley
- 出版日期: 2016-04-11
- 定價: $4,700
- 售價: 8.0 折 $3,760
- 語言: 英文
- 頁數: 304
- 裝訂: Hardcover
- ISBN: 111875011X
- ISBN-13: 9781118750117
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相關分類:
半導體、邏輯設計 Logic-design、電路學 Electric-circuits
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商品描述
Demonstrates techniques which will allow rewiring rates of over 95%, enabling adoption of deep sub-micron chips for industrial applications
Logic synthesis is an essential part of the modern digital IC design process in semi-conductor industry. This book discusses a logic synthesis technique called “rewiring” and its latest technical advancement in term of rewirability. Rewiring technique has surfaced in academic research since 1993 and there is currently no book available on the market which systematically and comprehensively discusses this rewiring technology. The authors cover logic transformation techniques with concentration on rewiring. For many decades, the effect of wiring on logic structures has been ignored due to an ideal view of wires and their negligible role in the circuit performance. However in today’s semiconductor technology wiring is the major player in circuit performance degeneration and logic synthesis engines can be improved to deal with this through wire-based transformations. This book introduces the automatic test pattern generation (ATPG)-based rewiring techniques, which are recently active in the realm of logic synthesis/verification of VLSI/SOC designs.
- Unique comprehensive coverage of semiconductor rewiring techniques written by leading researchers in the field
- Provides complete coverage of rewiring from an introductory to intermediate level
- Rewiring is explained as a flexible technique for Boolean logic synthesis, introducing the concept of Boolean circuit transformation and testing, with examples
- Readers can directly apply the described techniques to real-world VLSI design issues
- Focuses on the automatic test pattern generation (ATPG) based rewiring methods although some non-ATPG based rewiring methods such as graph based alternative wiring (GBAW), and “set of pairs of functions to be distinguished” (SPFD) based rewiring are also discussed
A valuable resource for researchers and postgraduate students in VLSI and SoC design, as well as digital design engineers, EDA software developers, and design automation experts that specialize in the synthesis and optimization of logical circuits.
商品描述(中文翻譯)
展示了能夠實現超過95%重接率的技術,使得深亞微米晶片能夠應用於工業應用
邏輯綜合是半導體產業現代數位集成電路設計過程中的一個重要部分。本書討論了一種名為「重接」(rewiring)的邏輯綜合技術及其在可重接性方面的最新技術進展。重接技術自1993年以來在學術研究中逐漸浮現,目前市場上尚無系統性和全面性討論此重接技術的書籍。作者專注於重接的邏輯轉換技術。數十年來,由於對導線的理想化看法及其在電路性能中微不足道的角色,導線對邏輯結構的影響被忽視。然而,在當今的半導體技術中,導線是電路性能退化的主要因素,邏輯綜合引擎可以通過基於導線的轉換來改善這一點。本書介紹了基於自動測試模式生成(ATPG)的重接技術,這些技術最近在VLSI/SOC設計的邏輯綜合/驗證領域中活躍。
- 由該領域的領先研究者撰寫的半導體重接技術的獨特全面覆蓋
- 從入門到中級水平提供重接的完整覆蓋
- 重接被解釋為一種靈活的布林邏輯綜合技術,介紹了布林電路轉換和測試的概念,並附有示例
- 讀者可以將所描述的技術直接應用於現實世界的VLSI設計問題
- 雖然也討論了一些非ATPG基礎的重接方法,如基於圖的替代接線(GBAW)和「要區分的函數對集合」(SPFD)基礎的重接方法,但本書重點在於基於自動測試模式生成(ATPG)的方法
本書是VLSI和SoC設計研究人員及研究生、數位設計工程師、EDA軟體開發者和專注於邏輯電路綜合與優化的設計自動化專家的寶貴資源。