Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology: Volume 2
暫譯: 集成電路實現、電路設計與製程技術的電子設計自動化：第二卷

Lavagno, Luciano, Martin, Grant, Markov, Igor L.

Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology: Volume 2
  • 出版商: CRC
  • 出版日期: 2026-06-29
  • 售價: $10,800
  • 貴賓價: 9.5 折 $10,260
  • 語言: 英文
  • 頁數: 781
  • 裝訂: Hardcover - also called cloth, retail trade, or trade
  • ISBN: 1032935707
  • ISBN-13: 9781032935706
  • 相關分類: 電路學 Electric-circuits

    • 海外代購書籍(需單獨結帳)

商品描述

Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology, the second of two volumes in the Electronic Design Automation for Integrated Circuits Handbook, Third Edition, thoroughly examines real-time logic (RTL) to GDSII generation, analog/mixed-signal design, physical verification, and technology computer-aided design (TCAD). Chapters contributed by leading experts authoritatively discuss design for manufacturability (DFM) at the nanoscale, power supply network design and analysis, design modeling, and much more.

New to This Edition:

  • Major updates appearing in the initial phases of the design flow, where the level of abstraction keeps rising to support more functionality with lower non-recurring engineering (NRE) costs
  • Significant revisions reflected in the final phases of the design flow, where the complexity due to smaller and smaller geometries is compounded by the slow progress of shorter wavelength lithography
  • New coverage of cutting-edge applications and approaches realized in the decade since the publication of the second edition--these are illustrated by updates including the impact of new analog layout methods, chiplet integration, and power-optimized design, in various chapters

Offering improved depth and modernity, this book provides a valuable, state-of-the-art reference for electronic design automation (EDA) students, researchers, and professionals.

商品描述(中文翻譯)

《電子設計自動化：集成電路實現、電路設計與製程技術》是《集成電路電子設計自動化手冊》第三版的兩卷中的第二卷，深入探討從實時邏輯（RTL）到GDSII生成、類比/混合信號設計、物理驗證及技術計算機輔助設計（TCAD）。各章節由領域內的專家撰寫，權威地討論納米尺度的可製造性設計（DFM）、電源網路設計與分析、設計建模等主題。

本版新內容：
- 在設計流程的初始階段出現的重大更新，抽象層次不斷提高，以支持更多功能並降低非重複工程（NRE）成本
- 在設計流程的最終階段反映出的重大修訂，由於幾何尺寸不斷縮小而導致的複雜性，與短波長光刻技術的緩慢進展相互交織
- 新增自第二版出版以來十年間實現的尖端應用和方法的內容，這些內容在各章中通過更新展示了新類比佈局方法、晶片集成和功率優化設計的影響

本書提供了更深的內容和現代性，是電子設計自動化（EDA）學生、研究人員和專業人士的寶貴、最先進的參考資料。

作者簡介

Luciano Lavagno received his Ph.D. in EECS from U.C. Berkeley in 1992 and from Politecnico di Torino in 1993. He co-authored two books on asynchronous circuit design, a book on hardware/software co-design of embedded systems, and over 250 scientific papers. Between 1993 and 2000 he was the architect of the POLIS project, a cooperation between U.C. Berkeley, Cadence Design Systems, Magneti Marelli and Politecnico di Torino, which developed a complete hardware/software co-design environment for control-dominated embedded systems. Between 2003 and 2014 he was one of the creators and architects of the Cadence CtoSilicon high-level synthesis system. Since 2011, Dr. Lavagno has been a full professor with Politecnico di Torino, Italy. He has served on the technical committees of several international conferences in his field (e.g. DAC, DATE, ICCAD, ICCD, ASYNC, CODES) as well as various workshops and symposia and is a senior member of IEEE. He has also been an associate editor of IEEE TCAS and ACM TECS. His research interests include the high-level synthesis of digital circuits and the acceleration of Machine learning algorithms using Field Programmable Gate Arrays.

Grant E. Martin retired from his position as a distinguished engineer at Cadence Design Systems, Inc., San Jose, California, USA, in 2023. Before that, Grant worked for Burroughs in Scotland for 6 years; Nortel/Bell-Northern Research in Canada for 10 years; Cadence Design Systems for 9 years, eventually becoming a fellow in their labs; and Tensilica for 9 years. He rejoined Cadence in 2013 when it acquired Tensilica, and has been there since, working in the Tensilica part of the Cadence Intellectual Property Group. He received his bachelor's and master's degrees in mathematics (combinatorics and optimization) from the University of Waterloo, Ontario, Canada, in 1977 and 1978. Grant has coauthored and coedited several books, including the first-ever book on system-on-chip (SoC) design published in Russian. He has also presented many papers, talks, and tutorials, and participated in panels at several major conferences. He cochaired the VSI Alliance Embedded Systems Study Group in the summer of 2001 and was co-chair of the Design Automation Conference Technical Program Committee for Methods for 2005 and 2006. He is a senior member of IEEE. Although retired, he continues to have an interest in system-level design, IP-based design of system-on-chip, platform-based design, DSP, baseband and image processing, and embedded software.

作者簡介(中文翻譯)

Luciano Lavagno 於1992年在加州大學伯克利分校獲得電子工程與計算機科學博士學位，並於1993年在都靈理工大學獲得博士學位。他共同撰寫了兩本有關非同步電路設計的書籍、一部關於嵌入式系統硬體/軟體共同設計的書籍，以及超過250篇科學論文。在1993年至2000年間，他是POLIS專案的架構師，該專案是加州大學伯克利分校、Cadence Design Systems、Magneti Marelli和都靈理工大學之間的合作，開發了一個完整的硬體/軟體共同設計環境，專為控制主導的嵌入式系統而設。2003年至2014年間，他是Cadence CtoSilicon高階合成系統的創建者和架構師之一。自2011年以來，Lavagno博士一直是意大利都靈理工大學的正教授。他曾擔任多個國際會議的技術委員會成員（例如DAC、DATE、ICCAD、ICCD、ASYNC、CODES），以及各種研討會和座談會，並且是IEEE的資深會員。他還曾擔任IEEE TCAS和ACM TECS的副編輯。他的研究興趣包括數位電路的高階合成以及利用現場可程式邏輯閘陣列加速機器學習演算法。

Grant E. Martin 於2023年從美國加州聖荷西的Cadence Design Systems, Inc. 退休，擔任傑出工程師。在此之前，Grant在蘇格蘭的Burroughs工作了6年；在加拿大的Nortel/Bell-Northern Research工作了10年；在Cadence Design Systems工作了9年，最終成為他們實驗室的研究員；以及在Tensilica工作了9年。他於2013年在Cadence收購Tensilica後重新加入該公司，並一直在Cadence智慧財產權集團的Tensilica部門工作。他於1977年和1978年在加拿大安大略省的滑鐵盧大學獲得數學（組合數學和優化）的學士和碩士學位。Grant共同撰寫和編輯了幾本書籍，包括第一本以俄文出版的系統單晶片（SoC）設計書籍。他還在多個主要會議上發表了許多論文、演講和教程，並參加了多個小組討論。他於2001年夏季共同主持了VSI Alliance嵌入式系統研究小組，並在2005年和2006年擔任設計自動化會議技術程序委員會的方法共同主席。他是IEEE的資深會員。儘管已退休，他仍然對系統級設計、基於IP的系統單晶片設計、平台設計、數位信號處理、基帶和影像處理以及嵌入式軟體保持興趣。

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