Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits (Hardcover)
暫譯: 高速A/D轉換的連續時間Δ-Σ調變器:理論、實踐與基本性能極限 (精裝版)
James A. Cherry, W. Martin Snelgrove
- 出版商: Springer
- 出版日期: 1999-09-30
- 售價: $8,860
- 貴賓價: 9.5 折 $8,417
- 語言: 英文
- 頁數: 250
- 裝訂: Hardcover
- ISBN: 0792386256
- ISBN-13: 9780792386254
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商品描述
Among analog-to-digital converters, the delta-sigma modulator has cornered the market on high to very high resolution converters at moderate speeds, with typical applications such as digital audio and instrumentation. Interest has recently increased in delta-sigma circuits built with a continuous-time loop filter rather than the more common switched-capacitor approach. Continuous-time delta-sigma modulators offer less noisy virtual ground nodes at the input, inherent protection against signal aliasing, and the potential to use a physical rather than an electrical integrator in the first stage for novel applications like accelerometers and magnetic flux sensors. More significantly, they relax settling time restrictions so that modulator clock rates can be raised. This opens the possibility of wideband (1 MHz or more) converters, possibly for use in radio applications at an intermediate frequency so that one or more stages of mixing might be done in the digital domain. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits covers all aspects of continuous-time delta-sigma modulator design, with particular emphasis on design for high clock speeds. The authors explain the ideal design of such modulators in terms of the well-understood discrete-time modulator design problem and provide design examples in Matlab. They also cover commonly-encountered non-idealities in continuous-time modulators and how they degrade performance, plus a wealth of material on the main problems (feedback path delays, clock jitter, and quantizer metastability) in very high-speed designs and how to avoid them. They also give a concrete design procedure for a real high-speed circuit which illustrates the tradeoffs in the selection of key parameters. Detailed circuit diagrams, simulation results and test results for an integrated continuous-time 4 GHz band-pass modulator for A/D conversion of 1 GHz analog signals are also presented. Continuous-Time Delta-Sigma Modulators for High-Speed A/D Conversion: Theory, Practice and Fundamental Performance Limits concludes with some promising modulator architectures and a list of the challenges that remain in this exciting field.
商品描述(中文翻譯)
在類比轉數位轉換器中,δ-σ調變器(delta-sigma modulator)已經在中等速度下佔據了高至非常高解析度轉換器的市場,典型應用包括數位音頻和儀器測量。最近對於使用連續時間迴路濾波器而非更常見的開關電容方法構建的δ-σ電路的興趣有所增加。連續時間δ-σ調變器在輸入端提供了較少噪聲的虛擬接地節點,對信號混疊具有內在保護,並且在第一階段有潛力使用物理而非電氣積分器,適用於加速度計和磁通傳感器等新穎應用。更重要的是,它們放寬了穩定時間的限制,使得調變器的時鐘速率可以提高。這為寬頻(1 MHz或更高)轉換器的可能性打開了大門,可能用於無線應用中的中頻,以便在數位領域進行一個或多個混合階段。
《高速度A/D轉換的連續時間δ-σ調變器:理論、實踐與基本性能極限》涵蓋了連續時間δ-σ調變器設計的各個方面,特別強調高時鐘速度的設計。作者從已知的離散時間調變器設計問題的理想設計出發,解釋了這類調變器的設計,並提供了Matlab中的設計範例。他們還涵蓋了連續時間調變器中常見的非理想性及其如何降低性能,並提供了大量有關非常高速度設計中的主要問題(反饋路徑延遲、時鐘抖動和量化器亞穩定性)及如何避免這些問題的資料。他們還給出了一個具體的高速度電路設計程序,說明了在選擇關鍵參數時的權衡。詳細的電路圖、模擬結果和針對1 GHz類比信號的集成連續時間4 GHz帶通調變器的測試結果也隨之呈現。
《高速度A/D轉換的連續時間δ-σ調變器:理論、實踐與基本性能極限》以一些有前景的調變器架構和該激動人心領域中仍然存在的挑戰清單作為結尾。