Synchronization and Arbitration in Digital Systems (Hardcover)

David J. Kinniment

  • 出版商: Wiley
  • 出版日期: 2008-03-01
  • 售價: $1,350
  • 貴賓價: 9.8$1,323
  • 語言: 英文
  • 頁數: 280
  • 裝訂: Hardcover
  • ISBN: 047051082X
  • ISBN-13: 9780470510827
  • 下單後立即進貨 (約5~7天)

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商品描述

Today’s networks of processors on and off chip, operating with independent clocks, need effective synchronization of the data passing between them for reliability. When two or more processors request access to a common resource, such as a memory, an arbiter has to decide which request to deal with first. Current developments in integrated circuit processing are leading to an increase in the numbers of independent digital processing elements in a single system. With this comes faster communications, more networks on chip, and the demand for more reliable, more complex, and higher performance synchronizers and arbiters. Written by one of the foremost researchers in this area of digital design, this authoritative text provides in-depth theory and practical design solutions for the reliable working of synchronization and arbitration hardware in digital systems.

The book provides methods for making real reliability measurements both on and off chip, evaluating some of the common difficulties and detailing circuit solutions at both circuit and system levels. Synchronization and Arbitration in Digital Systems also presents:

  • mathematical models used to estimate mean time between failures in digital systems;
  • a summary of serial and parallel communication techniques for on-chip data transmission;
  • explanations on how to design a wrapper for a locally synchronous cell, highlighting the issues associated with stoppable clocks;
  • an examination of various types of priority arbiters, using signal transition graphs to show the specification of different designs (from the simplest to more complex multi-way arbiters) including ways of solving problems encountered in a wide range of applications;
  • essential information on systems composed of independently timed regions, including a discussion on the problem of choice and the factors affecting the time taken to make choices in electronics.

With its logical approach to design methodology, this will prove an invaluable guide for electronic and computer engineers and researchers working on the design of digital electronic hardware. Postgraduates and senior undergraduate students studying digital systems design as part of their electronic engineering course will struggle to find a resource that better details the information given inside this book

商品描述(中文翻譯)

當今的處理器網絡,無論是在晶片內外,均以獨立時鐘運作,這需要有效的數據同步以確保可靠性。當兩個或更多處理器請求訪問共同資源,例如記憶體時,仲裁器必須決定首先處理哪一個請求。當前集成電路處理的發展導致單一系統中獨立數位處理元件的數量增加。隨之而來的是更快的通訊、更多的晶片內網絡,以及對更可靠、更複雜和更高效能的同步器和仲裁器的需求。本書由該領域數位設計的頂尖研究者之一撰寫,提供了有關數位系統中同步和仲裁硬體可靠運作的深入理論和實用設計解決方案。

本書提供了在晶片內外進行真實可靠性測量的方法,評估一些常見的困難,並詳細說明電路和系統層級的電路解決方案。《Synchronization and Arbitration in Digital Systems》還介紹了:

- 用於估算數位系統中平均故障時間的數學模型;
- 有關晶片內數據傳輸的串行和並行通訊技術的總結;
- 如何為本地同步單元設計包裝器的解釋,強調與可停止時鐘相關的問題;
- 各類優先權仲裁器的檢視,使用信號轉換圖展示不同設計的規範(從最簡單到更複雜的多路仲裁器),包括解決在各種應用中遇到的問題的方法;
- 關於由獨立計時區域組成的系統的基本資訊,包括對選擇問題的討論以及影響電子學中選擇所需時間的因素。

本書以其邏輯性的設計方法論,將成為電子和計算機工程師及研究人員在數位電子硬體設計方面的寶貴指南。研究生和高年級本科生在電子工程課程中學習數位系統設計時,將難以找到比本書更詳細的資源。